A 10-Bit Fully-Predictive ADC with Code-Recombination Algorithm in Transducing Sensor Node Signals

Abstract

This paper presents a novel energy efficient code-recombination analog-to-digital converter (ADC) for low power applications. Dynamic tracking algorithm, search forward procedure (SFP) and search backward procedure (SBP) are introduced in this manuscript. Also, to generate the test voltage sequence fed in comparator, a binary code factor (BCF) is presented. And a lookup table (LUT) for digitizing the output code is employed. To verify the algorithm, a 10-bit ADC is designed in 0.13μm CMOS process with a 0.6 V supply. Given a 41.5 Hz sinusoid signal, the proposed ADC exhibits 9.75 effective number of bit (ENOB) and 80.9dB spur-free dynamic range (SFDR) at 10k Hz sample rate. Given full-scale sinusoid signals whose frequency are under 160Hz, the ADC achieves 39–77.4nW power consumption with 2.19–10.8 bitcycles in average, respectively. Also, simulation result shows the DNL and INL is bounded at 0.117 and 0.245LSBs.