A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect

Abstract

This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (DAC)with optimum sizing of the current sources. The DAC has been designed in 0.18 a#x03BC;m CMOS n-well technology provided by National Semiconductor. The 10-bit DAC is segmented as 5+5, where the 5-LSB bits are implemented in binary and the 5-MSB bits are implemented in unary architecture. The matching of the unit current sources plays an important role in determining the overall linearity of the DAC. Static linearity of the DAC can be improved by using larger area of the current source transistors, sacrificing the dynamic performances. At high frequency the spectral performance of the DAC degrades due to the increased parasitic. In this work the current sources are designed with optimum sizes to achieve improved static as well as dynamic performances. In simulation, the DAC achieves a maximum DNL of 0.248 LSB and a maximum INL of 0.440 LSB. The DAC achieves a maximum spurious free dynamic range (SFDR) of 59.79 dB for 5.37 MHz signal in mismatch environment at 500 MSPS sampling rate. The DAC shows a Nyquist SFDR of 57 dB at 500 MSPS sampling rate with mismatch. The DAC consumes only 17.85 mW of power for Nyquist signal at 500 MSPS sampling rate with 1.8 V supply.