A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS

Abstract

This paper presents a high speed parallel segmented capacitive DAC that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. Compared to converters that use the conventional structure, the speed of converting one bit digital code can be 4 times faster while the power remains relatively low. In the switching procedure, a small capacitor array is used to determine the high weight codes. A parallel capacitor array structure is used to reduce the mismatch and kickback noise effect caused by the small capacitor array. A prototype 10-bit 150MS/s SAR ADC with the parallel segmented capacitor array is implemented in 65nm CMOS technology. The ADC achieves an SFDR of 83.77 dB and 9.78-bit ENOB with only 1.476mW power consumption at a 1.2-V supply, resulting in a figure of merit (FOM) of 11.19 fJ/conversion-step.