A 10-b 70-MS/s CMOS D/A converter

Abstract

A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than +or-0.5 LSB. The settling time to +or-0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm*1.87 mm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>