A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

Abstract

Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.