A 10.5-mW 60-GHz QVCO Employing Hybrid Back-Gate and Tail Inductive Coupling in 22-nm FD-SOI Technology

Abstract

This work introduces a Quadrature Voltage Controlled Oscillator (QVCO) that employs the proposed hybrid back-gate and tail inductive coupling technique. The implemented QVCO on silicon occupies a die area of 0.03 mm in 22 nm FD-SOI technology. The power consumption of the QVCO operating with a 1 V supply voltage is 10.5 mW which, to the authors’ best knowledge, is comparable to the state-of-the-art. The time and frequency domain measurement results in free-running mode show a Phase Noise (PN) of -112.1 dBc/Hz at 10 MHz offset from 60.2 GHz. The phase error throughout the whole tuning range is below 4.8 ∘. At 10 MHz offset, The QVCO in this work achieves FoM and FoMA of -177.5 dBc/Hz and -192.7 dBc/Hz, respectively. They are in line among the bulk CMOS mm-wave QVCOs, despite the challenges imposed by short channel effects in 22 nm FD-SOI technology.