A 104GHz–117GHz power amplifier with 10.4% PAE in thin digital 65nm Low Power CMOS technology

Abstract

This paper presents a wide band 110GHz power amplifier in thin digital 65nm Low Power (LP) CMOS technology. The amplifier consists of 4 stages of single-ended common source (CS) amplifiers with Shielded Microstrip Line (S-MSL) based inter-stage and input-output matching networks. To address the decoupling issue of single-ended stages, a compact decoupling structure based on distributed inter-digitized MOM capacitor is implemented. The full wave electromagnetic simulations of the decoupling structure show an input impedance of 0.47-j0.12 Ω at 110 GHz. The measured maximum small signal gain of the power amplifier is 17.8 dB at 109 GHz with a 3 dB bandwidth of 13 GHz (104–117 GHz). The OP1dB is 8.25 dBm, while the saturated output power is 9.6 dBm at 112.5 GHz with 10.4% power added efficiency (PAE). The amplifier occupies an area of 340×400µm2 including RF pads.