A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications

Abstract

This paper proposes a novel event-driven level-crossing ADC (LCADC) that highly improves power efficiency and accuracy compared to existing LCADC implementations. For applications with sparse signals such as ECGs, neural action potentials, etc., such LCADC can have a large data reduction at the ADC output. The new LCADC topology uses clocked comparators and event-driven adaptive clocking to overcome the high power consumption and signal-dependent distortion of regular asynchronous LCADCs. Due to the introduced clock, the ADC can seamlessly be integrated with any type of digital processing circuit, event-driven or conventional. Fabricated in a 40nm CMOS technology, it obtains 10.4 ENOB (this is the highest reported accuracy in literature). The ADC shows dynamic power consumption: it consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.38 \mu\mathrm{W}$</tex> for a 15 kHz full-scale sine wave, while it consumes only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.92 \mu \mathrm{W}$</tex> for a typical ECG signal. The peak Walden FOM of the ADC is 138 fJ/conv, an improvement of 35% in power efficiency beyond the state of the art. For an ECG application, the IC achieves a data reduction of 30%, clearly indicating that the LCADC can achieve a large power reduction at system level.