A 103 fJ/b/dB, 10-26 Gbps Receiver with a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

Abstract

High speed data links are widely adopted for system chips integration. Limited by the power budget and heat dissipation constraints, energy-efficient SERDES with small foot print are demanding to enable multi-lanes interconnects. Dual-loop clock and data recovery circuits (DL-CDR), which consist of a cascaded PLL with phase rotators (PR) to decouple the loop bandwidth of PLL and CDR, are prevalent in the past decade [1]. As the data rate of high-speed I/O keeps increasing, a high-resolution phase rotator is required to meet the stringent clock jitter requirements. Consequently, the clocking scheme becomes the dominant factor of power consumption in a high-speed transceiver. In order to generate low noise and evenly distributed multi-phase clocks, PRs consisted of cascaded phase interpolators (PIs) with injection locked oscillators (ILO) have attracted lots of research efforts recently [2]. Instead, a nested loop CDR (NL-CDR) incorporates only a single PR inside the PLL [3]. They minimize the number of employed PI, and remedy the difficulties of high-speed multi-phase clock distribution. Thus, the power dissipation for clocking can be drastically reduced and benefit from low-pass filtering of PLL system. Meanwhile, no additional frequency calibration loop is required in contrast to ILO based PRs. However, the loop delay of the PLL impedes high frequency jitter tolerance of NL-CDR. To overcome this drawback, this paper proposes a dual feedback nested Loop CDR (DF-CDR). By this means it demonstrates a jitter tolerance of 0.45 UI up to 200 MHz at 26 Gbps operation.