A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR

Abstract

Wake-up receivers (WuRxs) play an increasingly important role in event-based internet of things (loT) applications. The two critical properties of WuRx are high sensitivity and μW-level power consumption that enable massive deployments and long lifetimes. Heterodyne architecture attracts more interest due to its superior sensitivity performance compared to others [1]. Recent reports of the WuRx’s sensitivity are limited by -97 dBm [2] –[5]. [6] achieves -124 dBm sensitivity but at the cost of power and latency. In addition, [2], [4] –[6] require off-chip RF components for matching and restricting bandwidth. To address these challenges, this paper presents a 2.4 GHz binary frequency-shift keying (BFSK) heterodyne WuRx with low-power All-Digital Phase Locked Loop (ADPLL) and sharp intermediate frequency (IF) filtering. It achieves -102 dBm sensitivity with $2.2 \mu \mathrm{A}$ to $171 \mu \mathrm{A}$ power range at 16 s to 100 ms latency. It demonstrates a -27/-30 dB continuous wave (CW) signal to interference ratio (SIR) at 3/5 MHz offset from the carrier.