A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration

Abstract

A ring oscillator (RO) generates a multi-phase clock with a large tuning range in a small area, enabling a per-lane implementation in multilane communication applications. However, a high-frequency RO suffers from inferior phase noise, which is exacerbated by its high flicker-noise corner [1], being unsuitable to be a precision-timing clock source for a high-throughput interface. While injection locking widens the noise-suppression bandwidth of an RO-based phase-locked loop (PLL) [2], its effectiveness to overall jitter is limited only to those with low multiplication factors. By exploiting the accumulation-free nature of jitter in delay-locked loops [3], the reference multiplier in [4] generates a clean mid-frequency clock and then is cascaded to a high-frequency PLL, achieving a low output jitter despite a high multiplication factor. However, the background calibration for the large delay errors in the reference multiplier due to process, supply voltage, and temperature (PVT) variations necessitates an excessive settling time, which is in the order of a few milliseconds at worst. While the reference multiplier in [5] achieves very low noise, its calibration, which also requires a long settling time, should be preceded by a post-fabrication trimming. In [6], another viable method for reference multiplication is presented. However, the long calibration time remains unsolved due to the required low noise contribution of its calibration PLL. In this paper, we present a 100MHz-reference, 8GHz/16GHz RO-based injection-locked all-digital PLL (IL-ADPLL) that incorporates a reference octupler (8xREF) with a probability-based adaptive calibration algorithm. The presented algorithm enables a fast, accurate phase-error calibration both under startup and after sudden environmental disturbance, e.g., a supply hop.