A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction

Abstract

In today's fully-integrated converters, the integrated LC components dominate the chip-area and have become the major limitation of reducing the cost and increasing the current density. This paper presents a 100 MHz four-phase fully-integrated buck converter with standard package bondwire inductors and a flying capacitor (CFLY) topology for chip-area reduction, occupying 1.25 mm2 effective area in 0.13-μm CMOS technology. A four-phase operation is introduced for chip-area reduction with the cost penalty minimized by utilizing standard package bondwire inductance as power inductors. Meanwhile, an extra more than 40% chip-area saving is achieved by the simple but effective CFLY topology to take advantage of the parasitic bondwire inductance at the input for ripple attenuation. A maximum output current of 1.2 A is obtained by the four-phase operation, while only 3.73 nF overall integrated capacitors are required. Also, with the chip-area hungry integrated spiral metal inductors eliminated, the current density is significantly increased. 0.96 A/mm2 current density and 82.4% efficiency is obtained with 1.2 V to 0.9 V voltage conversion without using any off-chip inductors or advanced processes. The reliability is also verified by measurement with various bondwire inductances and configurations.