A 10 MS/s 11-bit 0.19 mm$^{2}$ Algorithmic ADC With Improved Clocking Scheme

Abstract

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19 mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13 mum thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.