A 10-MHz BW 77.9 dB SNDR DT MASH $\Delta\!\Sigma$ ADC With NC-VCO-Based Quantizer and OPAMP Sharing

Abstract

This paper presents a power efficient discrete-time (DT) multi-stage noise-shaping (MASH) delta–sigma analog-to-digital converter (ADC) in $0.18~\mu \text{m}$ CMOS process for wide band applications. A noise-coupled voltage-controlled oscillator (VCO)-based quantizer is used to achieve second or higher order of noise shaping. This structure is power and area efficient as well as simple to implement, since it consists mostly of digital blocks. A 2–2 MASH modulator has been implemented by employing the NC-VCO-based quantizer as the second stage. This helps to overcome the VCO nonlinearity issue, since it only processes the quantization error of the first stage, and improve the dynamic range (DR). The first stage is implemented as a second-order modulator in modified feedback (CIFB) architecture. It consists of two integrators and a 4-bit quantizer. For enhanced power efficiency, opamp sharing is used between the second integrator of the first stage and the adder of second stage. The adder is used to extract the quantization error and also to implement the second stage. The prototype ADC achieves a peak SNDR and SNR of 77.9 and 79.1 dB, respectively, over a 10-MHz bandwidth with a 160-MHz sampling rate. The total power consumption including output buffers, is 19.6 mW from 1.8 V/1.5 V supplies, resulting in Walden and Schreier figures-of-merit of 152 fJ/Conv and 168 dB, respectively.