A 10‐GHz bandwidth 45.5‐dB SNDR buffer with local feedback in 45‐nm CMOS

Abstract

A high-speed and low-power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high-speed circuits operating at 20 GS/s. This novel two-stage buffer is employed with bandwidth expansion and slew-rate enhanced techniques. An improved common-mode feedback circuit stabilizes the output common-mode voltage. This prototype buffer is fabricated in the 45-nm COMS process, and achieves 7.2 bit ENOB at 10-GHz input frequency with power consumption of 20.4 mW, load of 0.3 fF.