A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology

Abstract

This paper describes the design of a 10Gb/s output driver offering a constant output voltage swing level over process, voltage and temperature (PVT) variations. Output voltage swing level can be controlled by MOS resistances in the final output driver stage. The proposed architecture employs replica output driver to compensate output voltage swing level. The gate voltage of PMOS/NMOS in the main output driver, which is generated by comparing voltage swing level of the replica driver with the desired output swing level, makes output driver voltage swing level to be constant by adjusting MOS resistances in the final stage of the output driver. The low swing output driver can be achieved by the proposed architecture; it reduces the power dissipation by reducing the voltage swing on the load. The proposed output driver is implemented using 65-nm CMOS process and operates at 10Gbps data rate over 30cm FR4-model.