A 10 bit resolution, 80 msamples/sec. pipelined ADC architecture

Abstract

This work presents the analyses and design of a fast analog to digital converter architecture intended for high-speed data streaming applications such as the IEEE 802.11a wireless LAN. Since high conversion speed and high resolution are required, a pipelined topology is the architecture of choice for the ADC. Realized with fully-differential switched-capacitor circuits, this topology provides an optimal compromise between high component precision and high-speed circuit performance. With the gain boosting technique, high-gain and fast-settling opamps are designed for the seven pipeline stages. In order to optimize the die area and power consumption, a flash converter provides the final 3 bits of the conversion word. A 10-bit precision is ensured with a digital self-calibration process that cancels offset and gain errors. The ADC is fabricated in a 0.13 /spl mu/m standard analog CMOS technology. It occupies 0.35 mm/sup 2/ and the typical power dissipation is 42 mW.