A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC

Abstract

This paper describes the design of a random access memory (RAM) bank with a 0.35-μm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.