A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

Abstract

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-/spl mu/m CMOS process, the circuit occupies an area of 7.4 mm/sup 2/. The converter achieves a differential nonlinearity and integral nonlinearity of /spl plusmn/0.8 LSB and /spl plusmn/0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s.