A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC

Abstract

A 10-bit 200 MS/s pipeline ADC using the capacitor-sharing concept is presented. A charge-neutralization technique is proposed between the 1st and 2nd MDACs to mitigate the memory effect. To further enhance power efficiency, a reference precharge technique is proposed between the 2nd and 3rd MDACs. The prototype ADC in 90-nm low-power CMOS process exhibits an INL of + 1.59/-1.91 LSB and a DNL of +0.70/-0.75 LSB. Its ENOB is 8.53 bits at input frequency of 2 MHz and 8.05 bits at Nyquist input frequency with the conversion rate of 200 MS/s. It consumes 45.4 mW at 1.2 V supply and occupies an active chip area of 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .