Abstract
A 1-Mb flash EEPROM (electrically erasable and programmable read-only memory) with a 5.6- mu m*4.4- mu m cell is fabricated with a double-polysilicon, single-metal, n-well CMOS process. A double-diffused drain structure is used to reduce hot-electron degradation of n-channel peripheral devices. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations are internally controlled by a timer that is stabilized against temperature and voltage supply variations. Addresses and data are latched during program and erase operations. Internal pumps generate the high voltage for the erase operation. Six redundant rows and two redundant columns are provided to enhance yield. Flash EEPROM cells similar to the array cells are used as the programmable elements in the redundancy circuits. Process parameters are given. >
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