Abstract
This letter proposes a Sub-GHz digital polar power amplifier circuit, which is intrinsically linear and power-efficient. The architecture is based on a 1-bit Delta-Sigma Modulator (DSM) to achieve amplitude modulation without a lossy capacitor array, which improves efficiency. A deskewing circuit eliminates skew-induced non-linearity and improves the EVM without pre-distortion. The proposed 1-bit-DSM-based PA, integrated in a 65 nm CMOS process, achieves -36.5 dB RMS EVM and 24.1% PAE for a 10 MSymbol/s 1024-QAM modulated signal at 960 MHz carrier, without pre-distortion.
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