A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS

Abstract

A 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates redundancy, reassignment, and digital correction to reduce the complexity of analog functions and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator performance is decoupled from matching requirements, so that small and fast dynamic comparators can be used. New analysis discusses the optimum combination of random and deliberate comparator offset to achieve a target effective number of bits (ENOB). This prototype ADC has the highest ENOB and highest sampling frequency of any reported Flash ADC utilizing redundancy. A proof-of-concept prototype achieves no missing codes, 46.6-dB spurious-free dynamic range, and 6.05-bit ENOB at Nyquist input frequency. Fabricated in 90-nm digital CMOS, with a core area of 1.2 mm2, the device consumes 204 mW from a 1.2-V/0.9-V analog/digital supply.