A 1.44-mW, 1-MHz bandwidth continuous-time Σ∆ modulator with 10-bit ENOB in 130-nm CMOS

Abstract

A low-power, low-pass continuous-time sigma-delta A/D modulator with 1-MHz bandwidth is implemented in a 130-nm CMOS process. The circuit is targeted for an IEEE 802.15.4 direct conversion receiver operating in the 2.4-GHz band. It has a third-order feedforward single-loop filter and a 1-bit quantizer to minimize power consumption. Non-return-to-zero DAC pulse shaping is used to reduce sensitivity to clock jitter. Clocked at 64 MHz, the prototype chip achieves 62-dB peak SNR, ?70-dB peak THD, 63-dB dynamic range with an oversampling ratio of 32. The built-in anti-alias filter provides alias attenuation greater than 57 dB, which improves coexistence of the receiver with other devices that operate in the 2.4-GHz band. The circuit dissipates 1.44 mW from the 1.2-V supply and the active die area is 0.1 mm2.