A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection

Wideband continuous-time (CT) Delta-Sigma modulators (DSMs) generally demand multi-level digital-to-analog converters (DACs), which require a linearization technique to overcome the problem of component mismatches. Dynamic element matching (DEM) is a popular DAC linearization approach but can be challenging to implement in a wideband DSM, particularly when there are many DAC elements. In this manuscript, we introduce a 13-level switched-capacitor (SC) DAC achieving high linearity with a simple DEM that rotates three unit elements only and does not incur excess loop delay. In a traditional CT DSM, a DAC of the SC type increases the amplifier settling requirements and damages the alias rejection. Earlier works have shown that these problems can be solved if the CT DSM adopts a passive RC frontend. A 10-MHz bandwidth CT DSM is designed in the 65-nm CMOS technology to validate the proposed DAC. Simulations show that the DAC enables a spurious-free dynamic range greater than 87.7 dB and a signal-to-noise pulse distortion ratio greater than 80.5 dB under a 1% capacitor mismatch, a 2% reference voltage error, and process variations.

A continuous-time (CT) sigma-delta modulator (SDM) for condenser microphone readout interfaces is presented in this paper. The CT SDM can accommodate a single-ended input and has high input impedance, so that it can be directly driven by a single-ended condenser microphone. A current-sensing boosted OTA-C integrator with capacitive feedforward compensation is employed in the CT SDM to achieve high input impedance and high linearity with low power consumption. Fabricated in a $$0.35$$ 0.35 - $$\upmu$$ μ m complementary metal-oxide-semiconductor (CMOS) process, a circuit prototype of the CT SDM achieves a peak signal-to-noise-and-distortion ratio of 74.2 dB, with 10-kHz bandwidth and $$801$$ 801 - $$\upmu$$ μ W power consumption.

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.

A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter

Continuous time (CT) sigma delta modulators are mixed signal systems that are commonly simulated at a system level using SPICE macro modeling, solving differential equations, implementing difference equations based on impulse invariance and using Simulink. In this paper, the delta transform (forward Euler method), the bilinear transform (trapezoidal rule), the midpoint integration method, a variation on the use of impulse invariance and Simpson's rule are used to determine difference equations which are used to simulate CT sigma delta modulators. The accuracy and speed of these methods are compared to Simulink models of CT sigma delta modulators with respect to the modulator's signal to quantization noise ratio and the elapsed time of each simulation.

Recent progress in continuous-time (CT) Delta-Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.

In this paper, passive continuous-time (CT) Sigma Delta modulators are briefly reviewed and compared with conventional active CT Sigma Delta modulators. A fifth-order CT Sigma Delta modulator with a hybrid active-passive loop filter is realized with only three active integrators. The hybrid CT Sigma Delta modulator is robust to the excess loop delay, clock jitter, and RC product variations. The prototype chip is designed in a 0.25- mum CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype Sigma Delta modulator achieves a 68-dB dynamic range and a - 75 dB IM3 over a 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of $$0.08\,\hbox {mm}^2$$ 0.08 mm 2 . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is $$76\,\upmu \hbox {W}$$ 76 μ W from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.

The effect of certain fundamental nonidealities on the resolution of a continuous-time (CT) delta sigma modulator are examined in this paper. We start by talking about the equivalence between an ideal CT delta sigma modulator and its discrete-time (DT) counterpart, then consider the effect of quantizer/DAC propagation delay, clock jitter, and the recently-identified phenomenon of signal-dependent jitter on the ideal performance.

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) DeltaSigma modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT DeltaSigma modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the DeltaSigma modulator. The proposed DT modeling technique is validated (for both independent and accumulated clock-jitter errors) against accurate simulations in SIMULINK, using behavioral blocks developed to directly simulate RZ or NRZ DACs with clock jitter. It is subsequently applied to various CT DeltaSigma modulator architectures (low- pass and bandpass, with single-bit and multibit DACs) to study the relative effectiveness of different feedback-DAC pulsing schemes (NRZ, RZ, RZ with fixed on-time, and RZ with fixed off-time) in minimizing the modulator sensitivity to clock jitter. The performance of each architecture is compared as a function of clock jitter, thereby offering a valuable reference for selecting a rectangular feedback-DAC pulse shape when designing CT DeltaSigma analog-to-digital converters.

Multi-bit continuous time Sigma Delta ($\Sigma\Delta$) modulators are the necessary drivers of modern high speed and low power analog to digital conversion technology. The use of multi-bit quantization in a continuous Time $\Sigma\Delta$ modulator has been limited because nonlinearity in the DAC (Digital to Analog Converter) of a sigma delta modulator translates directly into nonlinearity of the entire modulator, producing a distorted output. Nonlinearity in the DAC modulates the quantization noise into the signal band, thus degrading its performance. It is desired to estimate this non-linearity and apply a correction to nullify its effects. In this paper, a non-invasive background calibration technique is presented for the mismatch estimation and correction of static mismatches in the feedback DAC elements of a continuous time sigma delta modulator. The proposed design can fit into an existing modulator deploying a multi-bit D.AC. It is demonstrated by simulations that the proposed design achieves over 100dB THD performance across 40MHz signal bandwidth for an OSR (Over Sampling Ratio) of 30. The architecture works well even for topologies with achieving very high performance.

In this paper a new approach for employing the digital signal processing capabilities in the design of the multi-bit continuous time (CT) Delta Sigma modulators (DSM's) is presented. It proposes the discrete time (DT) pre-filtering before the DAC for solving the known problems of the CT DSM's.

Continuous time (CT) sigma delta modulators are commonly simulated using SPICE macro modeling, solving differential equations, implementing difference equations based on impulse invariance and using Simulink. In this paper, the delta transform (or Euler's forward method), the bilinear transform (or trapezoidal rule), and Simpson's rule are used to determine difference equations which are used to simulate CT sigma delta modulators. The speed and accuracy of these methods are compared to Simulink models of CT sigma delta modulators with respect to the elapsed time of the simulation, the modulator's signal to quantization noise ratio (SQNR), and modulator's dynamic range.

In this paper the spectral density of the additive jitter noise in continuous time (CT) Delta-Sigma modulators (DSM) is derived analytically. Making use of the analytic results, extracted in this paper, a novel method for elimination of the damaging effects of the clock jitter in continuous time Delta-Sigma modulators is proposed. In this method instead of the conventional waveforms used in the feedback path of CT DSM's such as the non return to-zero, the return to-zero, and the half delay return to-zero, an impulse waveform is employed.

A MATLABTM toolbox for the design and simulation of continuous time (CT) and discrete time Sigma-Delta modulators is presented. The design of Sigma-Delta modulators is performed by placing the poles and zeros of the loop filter and estimating the resulting noise transfer function and signal transfer function. For this, the toolbox offers a graphical user interface for direct user interaction. Several additional functions, e.g. excess loop delay compensation, are made available to the designer. Further, the designed loop filter can be synthesized in CIFF and CIFB topology or CRFF and CRFB in the case of a bandpass modulator. Additionally, the toolbox offers the design of a closed loop Sigma-Delta sensor readout having the sensor as part of the loop filter. Furthermore, several typical non-idealities of CT Sigma-Delta modulators such as real opamp behavior, excess loop delay, and jitter, are simulated with a tremendously speed up via the application of the lifting approach.