A 1.2V 0.2mW 27MHz CMOS limiting amplifier using cross-coupled active load structure

Abstract

ABSTRACT This paper presents a 1.2 V 0.2 mW CMOS limiting amplifier (LiA) designed in both schematic and layout levels using 130 nm CMOS technology. A cross-coupled active load structure is used to provide high differential gain and low common mode gain for the design. A common mode logic (CML) to CMOS level conversion topology is used to convert the differential input signal into a single-ended output signal for the proposed design. The designed circuit generates clock signal and behaves effectively up to modulation index variation ≤0.3 for input signal variation up to 40mVp-p. A bandwidth of 27 MHz is chosen for the amplifier design and the measurement shows a differential gain of 60 dB with a power consumption of about 0.2 mW excluding power consumption in buffer stage.