A 1.2 V high‐speed low‐power preamplifier latch‐based comparator

Abstract

The power consumption of chips has emerged as a major concern with the increased integration of analog circuitry. This work focuses on a two-stage comparator based on a preamplifier with latch for a successive approximation analog-to-digital converter. In order to minimize power loss and delay time, the charge steering approach was used in the design of latch as well as preamplifier. The suggested comparator is simulated in SMIC 0.18-um process in comparison to the comparator without charge steering mode. The results reveal that the average power consumption is only around 22 uW for varied input voltage at a supply voltage of 1.2 V, which is relatively lowered by approximately 30%. Meanwhile, delay time is also reduced by about 25%.