A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS

Abstract

Oversampling and noise-shaping converters show superior efficiency in the state of the art. Still, true Nyquist-rate converters are needed e.g. for multiplexed or general purpose ADCs. Among Nyquist-rate converters, SAR ADCs have shown the best efficiencies, but to achieve high linearity and dynamic range (DR), they require sophisticated calibration techniques. Moreover, the large sampling capacitors set very strict requirements on the preceding ADC driver. It has been shown that the driver's power consumption can significantly exceed that of the ADC itself [1], thereby making simple comparison of ADC FoMs inadequate. Continuous-time (CT) incremental delta-sigma (I-△Σ) ADCs offer Nyquist-rate conversion, inherit the oversampling and noise-shaping characteristics of freely-running △Σ modulators, and their resistive input is easier to drive, which can significantly increase the system efficiency. Thus, they seem an advantageous architecture for Nyquist-rate converters. Still, I-△Σ ADCs are usually employed for very low speed applications.