A 0.8 dB insertion-loss, 23 dB isolation, 17.4 dBm power-handling, 5 GHz transmit/receive CMOS switch

Abstract

The highest performance to date of any switch using a CMOS process, with a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.