A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS

Abstract

This paper presents a hybrid ADC with low supply voltage circuit technique to improve conversion speed and power efficiency for high resolution ADC. The proposed hybrid ADC is based on a non-binary cyclic conversion stage with an embedded binary successive approximation register (SAR) sub-ADC. To achieve high linearity at low supply voltage, MSBs’ stage employs a 1-bit/step non-binary cyclic architecture with proposed low voltage ring amplifier. An embedded binary charge redistribution SAR ADC with low voltage dynamic comparator and asynchronous SAR logic is employed to convert the residue of cyclic stage, and hence to improve the conversion speed and power efficiency of ADC. Proposed hybrid ADC including substrate voltage control technique for low supply voltage is designed in 65nm SOTB CMOS technology. Simulated SNDR = 84.04dB (ENOB = 13.67bit) is achieved while a 65.7kHz sinusoid input is sampled at 526kSPS under the supply voltage of Vdd=0.7V. The simulation results show the effectiveness and feasibility of the proposed hybrid ADC to improve the conversion speed and power efficiency of high-resolution ADC at low voltage.