A 0.6-V 9-bit 1-MS/s Charging Sharing SAR ADC With Judging-Window Switching Logic and Independent Reset Comparator for Power-Effective Applications

Abstract

This brief presents a 9-bit energy-effective charge sharing (CS) SAR ADC by using judging window switching logic. The power consumption of the DAC is greatly reduced when the signal is within a predefined small window. An independent reset technique is properly designed to improve the power efficiency of the latch comparator. Fabricated in a 0.18-μm process, the 9-bit ADC occupies a die area of 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Through optimized design, a maximum 75% and 37% power savings are obtained in the DAC and comparator, respectively. The measured DNL and INL are less than +0.56/-0.59 LSB and +0.83/-0.74 LSB. Operating at 1 MS/s, the CS ADC provides an SNDR up to 54.0 dB and SFDR up to 75.6 dB for a full-scale signal @ 0.422 MHz while consuming 2.65 uW from a 0.6-V power supply, resulting in a figure of merit (FoM) of 6.4 fJ/conversion step. Thanks to the judging window power can scale down to 1.74 uW for further power savings for small amplitude signals.