Abstract
This paper presents an ASIC design of ultra-low power SAR ADC. To achieve ultra-low power, the proposed ADC operates at ultra-low voltage, deploying a single-ended structure and top plate sampling technique. In order to improve sampling circuit linearity at ultra-low supply voltage, a bootstrapped switch is developed. A non-binary redundant algorithm is applied to correct the inevitable decision errors in the first few conversion steps. The proposed ADC is fabricated in a 0.18μm CMOS process. From the measurement results, it consumes only 16nW and achieves SNDR of 50.4dB, which is equivalent to an 8.08 ENOB, with 1kS/s sampling rate at 0.5V supply voltage.
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