A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS

Abstract

A Duty Cycle Corrector (DCC) with wide operation frequency band, wide duty-cycle correction range, high duty accuracy and low power consumption performance is proposed in this paper. A dual feedback loop with differential input clock is added to reduce the impact of charge pump imbalance on circuit performance. The chopping technique is also introduced to improve the loop gain meanwhile suppress the DC offset in the feedback loop. Furthermore, a novel duty-cycle adjuster (DCA) with configurable load capacitance is presented to maintain the duty-cycle correction range in a wide frequency range. The proposed DCC is implemented in 65-nm CMOS process with 1-V supply voltage. Post-simulation results indicate that the DCC corrects the input duty cycle with a range from 20% to 80% to 50±0.7% in the 0.5-5 GHz frequency range. The maximum power consumption of the DCC is 0.32 mW when the input clock frequency is set to 5 GHz.