A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC

Abstract

A 0.4 V single cycle 75 kbit SRAM macro protected with a multi-bit upset (MBU) correcting circuit is fabricated in a 28 nm LP-CMOS process. The novel error correcting circuit (ECC) is capable of 3-bit adjacent error correction and 8bit adjacent error detection. Simulation results show that the code provides a 2.35x improvement in corrected soft error rate (SER) over a Bose-Chaudhuri-Hocquenghem (BCH) double error correcting (DEC) code at a raw-SER of 1300 FIT/Mb while requiring 3 fewer check-bits. Further an alternative 2-bit adjacent error correcting implementation provides an corrected-SER approximately equal to the BCH DEC code for the same check-bit overhead as a single error correcting double error detecting (SEC-DED) code in the same error channel. Measurement results confirm an average active energy of 0.015 fJ/bit and leakage current of 10.1 pA/bit.