A 0.1–5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS

Abstract

A 0.1-5GHz Software-Defined Radio (SDR) transmitter in 65nm CMOS is presented. The transmitter integrates a dual-mode power amplifier (PA) for 0.1-1.5GHz low-cost narrowband applications (such as Industry Specific Applications, 2G, ZigBee), while a three-sub-band pre-power amplifier (PPA) is used for 0.45-5GHz high performance wideband applications (3G, 4G and etc.). A digital-assisted I/Q imbalance calibration circuit is proposed ahead the TX chain to pre-compensate I/Q mismatch in IF and LO modules. Analog baseband utilizes power scalable technique to optimize power consumption among different modes. The transmitter achieves -63.9dBc image rejection ratio (IRR) and -56.9dBc LO leakage rejection. In narrowband modes, the dual-mode PA provides >19dBm output P1dB with >20% PAE in its linear mode, and 23.2dBm maximum saturation power with 60% peak PAE in the switching mode. In wideband modes, the PPA provides maximum 9dBm output P1dB. F urthermore, system verifications demonstrate 0.5% EVM for 905MHz GSM at 19.5dBm output power. And the transmitter achieves -42.6dBc ACLR and 1.4% EVM for 2.3GHz LTE20 at 6.2dBm output.