Abstract
A 0.1–1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm2 core chip area and 5.4–24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30–40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.
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