A 0.076mm<sup>2</sup> 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS

Abstract

A spread-spectrum clock generator (SSCG) is a cost-effective solution to reduce EMI, which has become a serious problem in high-speed systems. In applications such as serial links, display drivers and consumer electronics, SSCG is essential or strongly recommended. Control options such as frequency deviation (δ) and modulation frequency (f m ) help to satisfy these demands. Furthermore, efficient modulation-profile generation is critical for achieving further EMI reduction and lowering fabrication cost. PLL-based SSCGs are reported in [1–3]. The ΔΣ modulator (ΔΣM) controls the division ratio [1,2] and the phase information of phase detector (PD) [3] to generate a spread-spectrum clock. The self-referenced clock generator uses a capacitor array to generate a spread-spectrum clock [7]. However, they do not have a way to control δ and f m . Dual-loop direct VCO modulation [4] and digital period synthesizer with delay-line [5] are able to control δ and f m . However, [4] requires an additional VCO, which increases the power consumption by 2×, and [5] suffers from a large deterministic jitter through the delay-line and logic circuits. A triangular profile is commonly used in many SSCGs [1,3,4]. Though the implementation of a triangular profile is very simple, its performance is poor. The chaotic PAM modulation in [2] requires complex analog circuits. Recently, a piecewise-linear profile with SRAM was presented in [5]. However, the additional memory consumes a large amount of power and occupies a large area. This paper presents a frequency-locked loop (FLL) based SSCG with frequency-to-voltage converter (FVC) [6], that saves area and provides multiple δ with low bandwidth variation. A memoryless Newton-Raphson modulation profile with multiple f m is also described.