A 0.02 nJ self-calibrated 65nm CMOS delay line temperature sensor

Abstract

This paper presents an area and power efficient delay line based temperature sensor for on-chip monitoring. This sensor can be deployed in large numbers on a microprocessor chip to facilitate advanced thermal and power management techniques. The proposed self-calibration design eliminates the effort associated with two-point calibration commonly found in conventional temperature sensors. In addition, it saves digital decoding power by the use of both tab and counter decoding. Measurement results for a 65nm CMOS design show that the proposed temperature sensor consumes 0.02 nJ energy per conversion. It occupies an active area of 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a resolution of 0.5°C with errors within ±2.0°C over a temperature range from 20 to 80°C.