A 0.0043-mm2 Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO Using Load-Direct Droop Detector and Time-Based Load-State Decision

Abstract

Low-dropout regulators have been commonly employed in a system-on-chip architecture for better power efficiency. Especially, digital low-dropout regulators (DLDOs) capable of operating at a low supply voltage have been developed for their scalability and compactness. Recently, to improve the integration of the DLDOs, synthesizable architectures [1] –[4] and output-capacitor-free designs [2] –[5] have been presented. The fully-synthesized DLDO in [1] has a digital-code reference resulting in good robustness. However, since a circuit to detect a load state is not employed, a quiescent current is consumed inefficiently in a steady state. To determine the load state, the DLDOs employ multiple comparators (CMPs) [2], [5] or an analog-to-digital converter (ADC) [3], [4]. However, the multiple CMPs require many references leading to additional complexity while the ADC of which the precision is determined by the fixed PMOS-to-NMOS ratio draws a static current from V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</inf> . In this paper, a fully-synthesizable DLDO which precludes the use of an output capacitor is presented. The DLDO determines the load state using a single CMP, a single voltage reference, and a tunable delay line (DL) without an external clock. In addition, for full synthesizability, a droop detector is connected to the output load directly, which dispenses with additional passive components used in [2]. Besides, a settling time from a droop event is quite improved by using a coarse controller and a load-direct droop detector (LD-DD). The DLDO featuring the fully-synthesized capacitorless architecture offers a small chip area and high current density.