A 0.8nV/√Hz CMOS preamplifier for IC-magneto-resistive read elements

Abstract

State-of-the-art tape drives now employ MR heads to achieve increased bit density and speed-independent signal amplitude. In such systems, the preamplifier (PA) has to support simultaneous reading of up to four signals from up to eight magneto-resistive (MR) read elements. Hence, thermal considerations require a minimum power consumption architecture. Due to manufacturing and wear out, head impedances from 20 to 150 /spl Omega/ must be allowed. The need for optimizing the read elements operating point also requires the integration of four programmable low-noise current sources. To allow for backward compatibility, the PA should amplify very large input signals at low distortion levels. Previous PA designs make use of expensive BiCMOS technology, have no on-chip low-noise current DACs, and do all the signal processing in the voltage-mode. This paper describes how CMOS technology can be used to achieve sub-nVspl radic/Hz noise levels counting contributions from both the amplifier and the bias-current sources. It also describes how large dynamic range and high PSRR are achieved by combining current and voltage-mode signal processing. The actual chip designed contains four preamps, four bias DACs for the read elements, an 8:4 input multiplexer, and a serial interface. It is realized in 1.2 /spl mu/m CMOS technology. >