Abstract
The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
