A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS

Abstract

This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">op</sub> ) compared to the SC-VRM system, and an efficiency η ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">op</sub> and η match those predicted by system simulations thereby validating the energy models.