Abstract
A 0.5 V static master-slave D flip-flop (DFF) divider-by-2 is implemented with a 0.13 μm 1P8M RF-mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
