A 0.5–3.0 GHz SP4T RF switch with improved body self-biasing technique in 130-nm SOI CMOS

Abstract

A single-pole four-throw (SP4T) RF switch with charge-pump-based controller is designed and implemented in a commercial 130-nm silicon-on-insulator (SOI) CMOS process. An improved body self-biasing technique based on diodes is utilized to simplify the controlling circuitry and improve the linearity. A multistack field-effect-transistor (FET) structure with body floating technique is employed to provide good power-handling capability. The proposed design demonstrates a measured input 0.1-dB compression point of 38.5 dBm at 1.9 GHz, an insertion loss of 0.27 dB/0.33 dB and an isolation of 35 dB/27 dB at 900 MHz/1.9 GHz, respectively. The overall chip area is only 0.49 mm2. This RF switch can be used in GSM/WCDMA/LTE front-end modules.