A 0.2–3.3 GHz 2.4 dB NF 45 dB gain CMOS current-mode receiver front-end

Abstract

A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.