A 0.18 $\mu{\rm m}$ CMOS Self-Mixing Frequency Tripler

Abstract

A self-mixing frequency tripler with fundamental frequency between 6-7.3 GHz is built by cascading a doubler and a single-balanced mixer. The doubler and the mixer share a transconducting inductor to reduce the tripler core size when fabricated using the TSMC 0.18 μm RF mixed signal 1P6M process. When the input signal frequency is 6.5 GHz at the power level of 3 dBm, the measured conversion gain is - 9.5 dB, the HRR1 is 21.5 dBc, the HRR2 is 29 dBc, and the total dc power consumption is 18.8 mW.