A 0.016 mm2 0.26-$\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Abstract

Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 $\mu \text{W}$ /MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator’s delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50–300 MHz output frequencies from a reference clock in the range of 0.5–5 MHz. The DPLL occupies an active area of 125 $\mu \text{m}\times125\mu \text{m}$ and achieves ±0.33% period jitter while consuming 63.5 $\mu \text{W}$ at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 $\mu \text{W}$ /MHz at 0.8-V supply voltage.