A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Abstract

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.