95/05446 Comparison of sample preparation methods for the spectrophotometric determination of phosphorus in soil and coal fly ash

Abstract

The integration of submicron poly-emitter transistor technology with CMOS devices, scaled down to 0·8 μm, to enhance the operating performance of BiCMOS ASICs in the GHz range, is described. It enables incorporation of npn, NMOS and PMOS transistors, Schottky diodes, polysilicon resistors and lateral fuses. The proposed process can facilitate CMOS, TTL and ECL signal levels on the same chip. To make the process more consistent and easy, the 19 masking steps are incorporated; most of them are noncritical oversized implant masks. N+ and P+ buried twin wells are formed for low isolation spacings along with their respective N and P epitaxial layers, to eliminate latchup susceptibility.The process includes some special features to increase the layout density and to reduce the parasitic capacitances. This is achieved by using sidewall spacers for polysilicon, self aligned vertical npn transistor structures and undoped polysilicon trench isolations. To obtain high fT (cut-off frequency) in the npn bipolar transistor, P+ poly base, N+ poly emitter and shallow junctions are incorporated. Titanium salicidation of N+ and P+ polysilicon is proposed while, on the source-drain of MOS transistors, a 20 nm thick TiW barrier layer deposition is added. A multilayer interconnect technology is employed with tungsten plugging and gold metallization.The 125-step process has been simulated for oxidation, impurity drive-in schedules and 12 implantation schemes in order to optimize various impurity profiles. The 60 nm emitter junction depth and 160 nm base width have been controlled by mixed boron and arsenic ion implantation through a poly-emitter window. The profile of an npn bipolar device, generated by process simulator (SUPREM), is directly provided to the device simulator (SEDAN) to find various important dc characteristics. The calculated fT and early voltage of the bipolar device were more than 7 GHz and 17 V respectively. For ac analysis of the above device, an inhouse-made high-speed transistor package (HIBTRA) has been used to explain the sinusoidal and transient behaviour of the device.The submicron MOS devices have been first simulated on an inhouse device simulator (MOSKIT) to determine their characteristics such as drain current, subthreshold current, substrate current and also to compute various MOS parameters required for circuit simulation and threshold voltage adjustment implantation doses.