9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s

Abstract

High-precision current-measurement front-ends are widely used in various applications, such as photoplethysmography (PPG) recording by biomedical sensors and molecular-concentration detection by electrochemical sensors. They usually require a low noise level down to pA to monitor small signal variations and a wide input range over µA to avoid saturation caused by large input fluctuations. The low-noise-level and wide-input-range requirements typically result in a dynamic range (DR) greater than 120dB. Prior high-DR current measurement front-ends either operate in the time domain using a capacitive-feedback TIA to integrate the input current and then digitize the output voltage via a digital counter [1], or operate in the frequency domain using an Hourglass ADC [2] or asynchronous DFFs [3]. Such methods can reduce the noise level by extending the integration time but suffer from a low conversion frequency (F conv ) as a result. To extend the input range, DC cancellation servo loops [1] or predictive DACs [2] are adopted, but the limited loop bandwidth results in a slow settling or saturation when the signal experiences a rapid change. Utilizing these methods, the previous works achieved an effective DR of ~120dB at F conv of 300-500Hz. This work adopts a different approach of simply increasing the DR of a continuous-time (CT) incremental ADC (IADC) to 140dB without any of the aforementioned methods and achieve a high F conv of 4 kHz. While the noise level and input range of the current-input CT-IADC are both determined by the feedback DAC within the modulator loop, this high DR is realized by increasing the number of DAC MSBs to extend the input range and disconnecting the inactive DAC cells to remove their noise contribution. The noise level is further minimized by adding extra LSB bits so that only the small LSB cells are active when the input approaches 0. In this work, an 11b resistive DAC (RDAC) together with a 12b SAR quantizer are implemented to achieve an input range of 200µA. Meanwhile, a tri-level {−1, 0, +1} DAC with reset-then-open (RTO) operation is introduced to disconnect the MSB cells dynamically without the issue of inter-symbol interference (ISI). To linearize the 11b DAC, a hybrid mismatch error shaping (HMES) scheme which combines segmented noise-shaped scrambling (SNSS) [4] and mismatch error shaping (MES) [5] is presented. This IADC with on-chip voltage references consumes 1.011mW from 1.2V and achieves >200dB FoM with an integral non-linearity (INL) of 8ppm.